A cache memory coherency protocol is often used to ensure that when a processing core accesses a particular cache memory line, the processing core is working on the most recent version of the particular cache memory line. Write backs of cached data to the main memory require power and may affect the performance of a system when excessive write backs are needed.
A cache memory tag directory can be used to keep track of the cache memory lines. The cache memory tag directory can have modest associativity and can control many cache memories close to the processing cores. Although the cache memory tag directory is typically indexed by a hash array of the memory addresses, it is not possible for the cache memory tag directory to represent all the configurations of valid cacheable memory lines.
The cache memory tag directory controls the cache memory lines that are in the cache memories by issuing back-invalidate commands whenever a cache memory line must be evicted because it is an entry that corresponds to a cache memory line being held in one or more of the cache memories. To achieve good cache memory performance, the number of tag entries in the cache memory tag directory should be larger than the number of different cache memory lines that can be held in the union of all the cache memories controlled by the cache memory tag directory.